Sr. Staff Engineer - SoC Safety Architect
This role is currently open. See the posting.
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Role summary
Research, innovate and provide SoC architecture platforms and solutions for all SoC’s across QCT. Engage collaboratively across teams and organizational boundaries, including with Hardware design & Verification, Software, Product Management and Product Planning teams to create leading SoC-wide solutions that provide the best-in-class cost, performance, and power. Develop, model and prototype new system solutions and approaches across functional tech IPs that allow our hardware technologies to be used efficiently and allow our customers to make better use of our hardware. Conduct hands-on workload analysis including algorithm optimization and analysis of performance and/or power characterizations to help define our SoC architecture solutions. Deploy simulators, profilers, and hardware solutions to provide quantitative justification for architectural directions. Efficiently communicate experimental results, review with technical leads and peers, and analyze outstanding issues. Innovate and develop new cross-IP SoC-wide solutions that enable existing and emerging market SoCs to meet their separate, unique product requirements for these technology areas: Power System, Shared Resource Management, Limits/Thermal Management, Hardware Islands, Debug, Safety, ARM Compliance, Exclusive Monitors and Far Atomics, Coherency, Memory Ordering, Memory Management, Virtualization, Control Processors, Signaling, Compression, Streaming, Always-On and system level ML.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Science, or related field and 6+ years of Systems Engineering or related work experience.
Master's degree in Electrical Engineering, Computer Science, or related field and 5+ years of Systems Engineering or related work experience.
PhD in Electrical Engineering, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.
- 2+ years of experience in one or more system architecture technology areas and products (e.g., Power System, Shared Resource Management, Limits/Thermal Management, Hardware Islands).
Nice to have
- SOC Architecture and Subsystem architecture deep understanding of one or more subsystems including CPU, GPU, AI Accelerators, Display Controllers, Camera Pre-processor, Infrastructure blocks (DDR, NOC, SMMU etc.) and I/O blocks (PCIe, ETH, CAN, Serial I/O)
- Ability to work with Subsystem Architects and Design leads to analyze failure modes of Subsystems when safety use cases execute and are mapped to these heterogenous compute subsystems
- Knowledge of SOC Infrastructure IP functionality including DDR controllers, NOC/Internal SOC interfaces, Power Management Control, BIST Control
- Knowledge of Safety Feature and Safety Mechanism design (requirements to integration/execution) for high performance, low power SOCs used in ADAS, ADS and IVI systems
- Prior experience with architecture or design or programming of one or more of common Instruction Set Architectures – x86, ARM, RISC V, MIPS etc.
- Hands-on experience with applying either ISO26262 or IEC61508 safety standards to complex SOCs for Auto or Industrial Safety applications
- Systems Safety Architecture experience to breakdown complex system safety use cases to requirement decomposition at SOC, AI Accelerators, DRAM, PMIC, MCU, Sensors etc.
- Ability to understand SOC and Subsystem level design functionality to analyze safety/failure mode implications of new functions, features added in design.
- Ability to understand and make appropriate safety recommendations to SOC and HW/SW Design teams when HW/SW/System issues or HW bugs are found during project execution.
- Prior experience developing, innovating, or optimizing (power/performance/safety) safety features, freedom from interference features at SOC or System
- Experience developing System and SOC level safety concepts and SEooC work products as per ISO 26262Road Vehicles - Functional Safety. Automotive functional safety standard defining ASILAutomotive Safety Integrity Level (A to D) under ISO 26262, derived from severity, exposure, and controllability. Read more levels and the automotive safety lifecycle. Read more
- Experience developing formal safety requirements and assumptions of use at different levels of abstraction including System, SOC level, Subsystem level.
- Prior experience developing or contributing to Safety Manuals at device level SOCs, PMICs, DRAMs, MCUs
- Prior experience performing architecture level safety analysis using FMEAFailure Modes and Effects Analysis: a bottom-up method cataloging how components fail and what effects those failures produce. Read more, FTA, DFA and other common techniques
- Prior experience developing and understanding of quantitative safety analysis work products specifically FMEDAFailure Modes, Effects and Diagnostic Analysis: quantitative failure analysis producing safe/dangerous failure rates and diagnostic coverage. Read more at device level, subsystem level (CPU, GPU, AI accelerator etc.)
- Understanding of HW safety development lifecycle and HW safety development processes as per ISO 26262 or IEC 61508Functional Safety of E/E/PE Safety-Related Systems. The umbrella functional safety standard defining the safety lifecycle, SILA discrete level (SIL 1 to SIL 4) specifying the required risk reduction and dependability of a safety function under IEC 61508 and its sector standards. Read more levels, and requirements for electrical, electronic, and programmable systems. Read more
- Familiarity with one or more formal requirements development tools – JAMA, Codebeamer, DOORs, etc.
- Prior experience working with OEMs, Tier1s, other ecosystem partners for explaining System/SOC safety concepts, safety architecture and being able to represent the Company in safety arch meetings with customers.
- Prior experience in driving and/or support internal safety audits and external safety assessments with 3rd party safety assessors.
- Ability to work with domain experts and various stakeholders for SOC projects (SW, Power, Thermal, Security etc.)
- Prior experience in SOC RTL design, verification or post-si validation.
- Prior experience with Safety OS (e.g. QNX RTOS, Safe RTOS), AUTOSAR or Safety SW development for safety critical applications (Auto, Industrial, etc.)
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